详细介绍

BERT428 100G BERT 误码率测试仪

类别：

误码仪
品牌：

LUCEO

LUCEO BERT428是由速率从2Gbps到28.05Gbps的4通道高速码型发生模块组成及25Gbps到28.05Gbps的4通道误码检测模块，模块可以串联时钟工作，因此它是100Gb/s和未来400Gb/s应用的理想测试解决方案。

BERT428 is 100Gb/s BERT. EPG428 is an Electrical Pattern Generator module that plugs into the PARALLEX® Chassis. EPG428 can generate 4 channel electrical data from 1 Gb/s up to 29 Gb/s continuously. EED428 is an Electrical Error Detector module that plugs into the PARALLEX® Chassis. EED428 can check 4 channels electrical data from 22.0 - 28.2Gbps and 8.5Gb/s – 14.1Gb/s.

EPG428 Key Spec

PARAMETER	SYMBOL	VALUE	UNIT	NOTE
channels	chNo	4
Data Rate	DR	1… 29	Gbps	1)
Data Format		NRZ
PRBS Pattern		9, 15, 31
Differential Data Output Amplitude	DOutP/N	200…800	mVpp	setting range, 3)
Output Jitter (RMS)	Jrms	200	fs	Typical, 2)
Single ended Data Output Impedance	ZOse	50	W	Typical
Data Output Termination		AC - coupled
Clock Input / Output Frequency	FClk	0.5…14.5	GHz
Clock Input / Output Termination		AC - coupled

Note:

Output of clock signal is used for daisy chaining additional modules. Maximum daisy chain length is four.
RJ measured with CLK pattern. Depends on applied clock signal (measured with CLK20-2 Module, RJ=200fs)
Measured at 1GBd at the static High/ Low level of the signal with de-emphasis=0dB.
The eye height at higher data rates might differ.

EED428 Key Spec

PARAMETER	SYMBOL	Min	Max	UNIT	NOTE
Channels	chNo		4
Data Rate	DR	8.5 22.0	14.1 28.2	Gbps	1)
Data Formats		NRZ
PRBS Pattern		7, 9, 15, 23, 31
Differential Data Input Amplitude	DOutP/N	200	1200	mVpp	3), 4)
Differential Data Input Impedance	ZOse	90	110	W
Data Input Termination		AC - coupled
Clock Input / Output Frequency	FClk	12.8	14.2	GHz	2)
Clock Input / Output Termination		AC - coupled

Note:

Apply full rate clock for low data rate range and half rate clock for high data rate range.
Additional DR/40 CLK output installed
BER of better than 1E-12 can only be achieved if at least the min. input voltage level is applied
Minimum input voltage to guarantee error free detection (BER < 10-12) at PRBS31. The input sensitivity of
the module will be better for input signals with lower bandwidth, e.g. PRBS7.

EPG428

Data Rates 1 to 29 Gbps
4 channels
Operates with half rate clock
Differential Electrical Pattern Generator (K Connector)
Reference clock output to drive SERDES, CDR
that require low speed clock
PRBS pattern: 9, 15, 31
Data output polarity swap
High speed Clock Input and Output
GPIB/LAN/USB Interface
via PARALLEX® Chassis.
Small size: width 50.8mm (2”)

EED428

Data Rates 22.0 - 28.2Gbps and 8.5Gb/s – 14.1Gb/s Gbps
4 channels
Integrated individual CDR on each channel to track incoming data
Operates with half rate clock
Differential Electrical Error Detector (K Connector)
Reference clock output to drive SERDES, CDR
that require low speed clock
PRBS pattern: 7, 9, 15, 23, 31
Data input polarity swap
BER detection down to 1E-15
High speed Clock Input and Output
GPIB/LAN/USB Interface via mainframe
Small size: width 50.8mm (2”)

产品简介

详细介绍

BERT428 100G BERT 误码率测试仪

EPG428 Key Spec

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EED428 Key Spec

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EPG428

EED428